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FlexPhase™ Technology
FlexPhase™ technology anticipates the phase difference between signals on different traces and manages the transmission of bits so that data arrives at the memory device with a known timing relationship relative to the command and address (C/A) signals. FlexPhase circuits can be used on a per device or a per pin basis. At gigahertz data rates, FlexPhase technology allows memory interfaces to operate without the power, area and latency penalties incurred when using Clock and Data Recovery (CDR) techniques. In addition, FlexPhase technology eliminates the need for PCB trace-length matching and compensates for manufacturing variations. With all these advantages, FlexPhase technology enables more robust, lower-power, compact and cost-efficient memory system implementations. Learn more.
DRAM Micro-threading
Micro-threading improves the transfer efficiency and effective use of DRAM devices by reducing access granularity. It allows minimum transfer sizes one quarter that of typical non-threaded DRAM devices. This is accomplished in Micro-threading by using independent row and column circuitry for each quadrant of physical memory space. Independent addressability of each quadrant complements the threaded memory workload needs of modern graphics and multi-core processors. Absent Micro-threading, prefetch lengths have been extended to allow DRAM core speeds to keep up with interface speeds. However, as a result, DRAM cores are increasingly inefficient at transferring useful data. Micro-threading maintains total data bandwidth of each device, improves transfer efficiency and reduces power consumption per transaction. Learn more.
Dynamic Point-to-Point Technology
Conventional memory buses in PCs and servers use multi-drop data topologies that support upgradeability by allowing multiple modules to be plugged into the bus. However, multi-drop topologies have degraded signal integrity as speeds increase which limits the number of modules the bus can support. Conversely, point-to-point topologies (one device at each end of the signal line) have better signal integrity and support higher bus speeds, but cannot be upgraded because they do not allow multiple modules. Dynamic Point-to-Point (DPP) technology combines the benefits of both point-to-point and multi-drop topologies, allowing the creation of memory systems using robust point-to-point signaling with the flexibility to add memory capacity through module upgrades. In addition, DPP technology maintains full memory system bandwidth across all supported configurations. DPP won an EDN Innovation of the Year Award. Learn more.
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32X Data Rate
Rambus' 32X Data Rate technology enables extremely high data rates and device bandwidths while maintaining relatively low system clock speeds. As an example, with 32X Data Rate technology, signaling rates of 25.6Gbps can be achieved with an economical 800MHz system clock. In a 4-byte wide configuration, this would provide a bandwidth of over 100GB/s from a single DRAM device. 32X Data Rate was developed through Rambus' Terabyte Bandwidth Initiative (TBI). TBI demonstrates the technologies enabling a memory architecture that can deliver a terabyte (1024 gigabytes) of memory bandwidth to a single SoC such as a microprocessor or GPU.
FlexClocking™ Architecture
Multi-gigahertz memory interfaces normally require timing synchronization circuitry in both the controller and memory interface in order to compensate for any skew that arises between clock, data, and C/A signals. The FlexClocking™ architecture places critical calibration and timing circuitry in the controller interface while greatly simplifying the design of the DRAM interface. The clock is forwarded and distributed to both the controller circuit blocks and the DRAM device from a central PLL located in the memory controller interface. With this innovative architecture, the need for a DLL or PLL on the DRAM is eliminated, simplifying DRAM design and greatly lowering memory power consumption. The FlexClocking architecture was developed through Rambus' Mobile Memory Initiative [link] which demonstrated technologies enabling a high-bandwidth, low-power memory architecture for mobile products. Learn more.
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