16X Data Rate

Rambus' 16X Data Rate technology enables extremely high bit-transfer rates and per device bandwidth while maintaining relatively low system clock speeds. As an example, with 16X Data Rate technology, signaling rates of 12.8Gbps can be achieved with an 800MHz system clock. In a 4-byte wide DRAM device, this provides a device bandwidth of 51.2GB/s. Since very high bandwidths can be achieved per device, this implies fewer devices are required to meet a target performance level, reducing needed board area and controller-side interface width. These enable lower system complexity and costs.

Background

Graphics processors, game consoles and multi-core processor-based PCs are driving the demand for increased memory bandwidth. The memory bandwidth demands for games consoles have increased dramatically from less than 1GB/s in 1995 to 50GB/s in the current generation of game consoles. Next-generation game consoles are projected to require more than 300GB/s of memory bandwidth to meet the expectations of game developers and consumers.

The graphics card market has shown a similar trend with system bandwidth demands rising from less than 1GB/s in 1995 to over 100GB/s today. It is anticipated that next-generation graphics cards will need more than 500GB/s of memory bandwidth early in the next decade.

Today's memory bandwidths are achieved using conventional double data rate (DDR) or quad data rate memory systems and wide parallel busses. Because of the challenge of adding more channels and I/O pins, the use of wide busses in future applications will be increasingly expensive and difficult to scale. Wide busses also consume a significant amount of power.

Rambus' 16X Data Rate technology proposes a different approach. It offers a scalable migration path to faster memory and higher resulting device bandwidth with fewer wires and more efficient use of I/O pins. This reduces complexity, power consumption and cost.

Implementing 16X Data Rate technology is challenging and requires a supporting foundation of innovations. Rambus addresses these challenges through its Jitter Reduction Technology, Asymmetric Equalization, and Enhanced FlexPhase™ calibration.

What is 16X Data Rate Technology?

16X Data Rate technology transfers 16-bits of data per I/O on every clock cycle, achieving a data rate of up to 12.8Gbps with an 800MHz system clock. In comparison, a GDDR5 memory system transfers four bits of data per I/O for every clock cycle providing 3.2Gbps transfer rate using the same 800MHz clock. With 16X Data Rate technology, twice the data rate can be achieved using a system clock that runs only half as fast as required in a GDDR5 system.

It is extremely difficult to achieve data rates of up to 12.8Gbps while maintaining signal integrity. At these data rates, one bit is transferred in just 78.1 picoseconds, so Jitter Reduction Technology is important if the Bit Error Rate (BER) is to be kept below an acceptable threshold of 10-15 (one bit error for every 1015 bits transferred).

What is Jitter Reduction Technology?

Jitter is the variation of a signal's amplitude, phase, bit width or bit position from its ideal position. It is a particular problem in high-speed systems because even small variations can cause significant timing errors and increase the BER.

16X Data Rate technology utilizes several jitter reduction technologies:

• LC Phase Locked Loop (PLL) clocking architecture – the resonant tank circuit, an inductor and capacitor tuned to a fundamental frequency, has lower phase noise than a traditional ring oscillator. This oscillation scheme results in more stable clock edges and reduced jitter while providing frequency multiplication up to the target data rate;
• Localized feedback loops – feedback loops are kept closer to the transmitter and receiver to shorten signal wiring;
• Reduced buffer size;
• Top-level clock distribution uses AC-coupled CML-to-CMOS conversion to reduce power-supply induced jitter, while keeping power consumption to reasonable levels;
• Regulated power supplies for the VCO and front-end circuits help to reduce noise levels in the most sensitive circuit paths.

In addition to these jitter reduction technologies, Rambus' 16X Data Rate technology employs Asymmetric Equalization and Enhanced FlexPhase™ timing adjustments.

Asymmetric Equalization counteracts the tendency for FR4 system boards to attenuate higher frequencies more than lower frequencies. Asymmetric Equalization is also useful at multi-Gbps data rates to offset the inter symbol interference (ISI) - interference to the current bit from the residual energy of a previous bit- that would otherwise dramatically degrade signal integrity.

Asymmetric Equalization uses a multi-tap transmit FIR (Finite Impluse Response) filter combined with a programmable receive linear equalizer to perform the equalization functions. The optimum equalization coefficients can be predicted through analysis of a given board and package design, and can be refined via an adaptive algorithm during the system initialization sequence. Responsibility for the majority of the equalization functions is placed on the controller, which helps reduce required DRAM complexity and cost.

Asymmetric Equalization results in a linear output across the frequency range enhancing signal integrity at multi-Gbps data rates.

FlexPhase timing adjustments compute the optimal transmit and receive phases of each link from the controller to the DRAM based on real-time measurements of the system phase response.

For 16X Data Rate technology, FlexPhase calibration has been enhanced with improved linearity and sub-picosecond resolution. The controller calibrates optimal transmit and receive phase values by transmitting a test pattern across a range of phase settings and registering the boundaries between failing and passing regions. The transmit and receive phases are then placed half way between these boundaries to maximize the timing margin.

Enhanced FlexPhase calibration compensates for any static offsets and other sources of deterministic jitter in the package or PCB, simplifying DRAM design, and, by permitting variable length traces, reducing PCB complexity and area.

The effects of Jitter Reduction Technology, Asymmetric Equalization and Enhanced FlexPhase timing adjustments can be seen in the following before and after eye diagrams.

Commercial and Performance Benefits

• 16X Data Rate Technology is a scalable alternative to wider busses for applications requiring high speed memory;
• 16X Data Rate Technology uses fewer wires more efficiently by transferring 16-bits per clock cycle, simplifying memory architecture, reducing power consumption and decreasing hardware costs;
• Jitter Reduction Technology, Asymmetric Equalization and Enhanced FlexPhase timing adjustments aid signal integrity at multi-Gbps transfer rates and make 16X Data Rate technology feasible.