Memory System Challenges in the Multi-Core Era
Visit Denali's website to hear Stephen Woo's MemCon 2008 presentation, Memory System Challenges in the Multi-Core Era.

Micro-threaded Row and Column Operations in a DRAM Core
The technique of micro-threading may be applied to the core of a DRAM to reduce the row and column access granularity. This results in a significant performance benefit for those applications that deal with small data objects. Read more...

Feasibility Study of a 3.2Gb/s Memory Interface in Ultra Low-Cost LQFP Packages
The feasibility of implementing a 3.2Gb/s XDR™ memory interface using an ultra low-cost LQFP package is analyzed. The target application includes multimedia electronics such as set-top boxes and HDTVs. Due to the large inductance of the ...

Modeling and Correlation of Supply Noise for a 3.2GHz Bidirectional ...
This paper describes the modeling of power supply noise in a high-bandwidth XDR™ DRAM memory system and the correlation with measurement results in time domain while the system is operating. A supply network model is presented that ...

Novel Test Infrastructure and Methodology Used for Accelerated Bring-up and ...
Design-for-test (DFT) techniques are continuously used in designs to help identify defects during silicon manufacturing. However, prior to production, a significant amount of time and effort is needed to bring-up and validate various ...

The Design and Signal Integrity Analysis of a TB/sec Memory System
The design and signal integrity analysis of a Terabyte per second (TB/sec) memory system is presented in this work. The interface technology utilizes a bi-directional low swing differential signaling with a data transfer rate of 16 ...

DDR3 Memory Controller Interface Brief
As the computational power of silicon chips continues to ramp, memory interfaces become increasingly critical to system performance. As a result, the signaling frequencies of mainstream DDR DRAMs have steadily increased, making the ...

Creating a Generic Behavioral Model – DDR based memory system using SystemC/TLM
In a typical design cycle, the behavioral models represent an executable architecture to be used for architectual explorations and performance analysis, as well as in customer simulations. They are required to stay ahead of RTL with ...

Power Integrity Analysis of DDR2 Memory Systems during Simultaneous ...
Simultaneous switching noise (SSN) in systems using single ended drivers poses significant design challenges as data rates continue to increase. In this paper, we analyze the impact of SSN on a DDR2 memory system using a wire-bond ...

XDR™ Clock Generator
The XDR™ Clock Generator provides the necessary clock signals to support XDR memory subsystem and Redwood logic interface using a reference clock input with or without spread spectrum modulation. Contained in a 28-pin TSSOP package that ...

XDR™ Memory Controller Interface Brief
The Rambus XDR DRAM achieves an order of magnitude increase in DRAM bandwidth over today's best-of-class memory systems. The XDR Interface uses a small number of very high-speed signals to carry all address, data, and control ...

XDR™2 Memory Architecture
Today's powerful graphics and multi-core processors require significantly higher memory performance when compared to traditional single-core processors. Without adequate data bandwidth, memory becomes the limiting factor in delivering ...

XDR™ IO Cell
The Rambus XDR™ IO Cell (XIO) is a high-performance, low latency controller interface to XDR-based DRAM memory systems. The XIO is a versatile CMOS macro cell that can be seamlessly integrated into a wide variety of target processes. The...

XDR™ Architecture
Rambus XDR™ technology has been designed to support a broad range of applications and component implementations spanning multiple technology generations. The XDR architecture comprises three primary semiconductor components: XDR DRAM XDR...

GDDR Memory Controller Interface Brief
Graphics and multimedia applications require high memory bandwidth to render life-like 3D images and buffer the large amount of frame data for image and video processing. In these applications, higher memory bandwidth translates directly...

XDR DRAM 8x4Mx16/8/4/2
The Rambus XDR™ DRAM device is a general-purpose high-performance memory device suitable for use in a broad range of applications, including computer memory, graphics, video, and any other application where high bandwidth and low latency...

Assessing Memory Bandwidth Needs for Next-Generation Digital TVs with ...
Authored in conjunction with Philips Consumer Electronics The most common memory solutions for designing high-performance consumer DTV systems are XDR™ and DDR2. Both these consumer DRAM memories are available from top suppliers ...

DDR Memory Controller Interface Brief
As the computational power of silicon chips continues to ramp, memory interfaces become increasingly critical to system performance. As a result, the signaling frequencies of mainstream DDR DRAMs have steadily increased, making the ...

XDR™ DRAM Product Brief
The Rambus XDR DRAM achieves an order of magnitude increase in DRAM bandwidth over todayʼs best-of-class memory systems. The XDR DRAM interface uses a small number of very high-speed signals to carry all address, data, and control ...

XDR™ Technology Summary
The Rambus XDR DRAM achieves an order of magnitude increase in DRAM bandwidth while using the fewest ICs. The XDR Interface uses a small number of very high-speed signals to carry all address, data, and control information. XDR ...