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File Name: A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications

Present-day computing systems require very high off-chip communications bandwidth, and multi-Gb/s serial links for chip-to-chip interconnect are now ubiquitous. As system designers face hard power limits due to thermal or battery-life requirements, optimizing power versus performance becomes more critical. Backplane transceivers have been demonstrated at about 20mW/Gb/s [1], and chip-to-chip links have more recently achieved power efficiencies near 10mW/Gb/s [2]. A further significant advance in power efficiency for these links is possible without sacrificing the jitter performance or signal integrity features required to operate at an acceptable BER.

This paper presents a 6.25Gb/s NRZ transceiver in 90nm dualgate (1.0V, 2.5V) CMOS designed to satisfy modest channel requirements with mesochronous timing. The transceiver dissipates 2.2mW/Gb/s, a 3.4× improvement of the power efficiency reported in [3]. The test chip includes 4 transceivers with shared LC-PLL, a support block with 4 PRBS generator/checkers, and an interface to an external controller. Power reduction is achieved using a shared LC-PLL for reference-clock multiplication, a resonant clock-distribution network, a low-swing voltage-mode transmitter, a low-power phase rotator for the receiver clocks, and software-based CDR and adaptive equalization.

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