創新

擁有超過 15 年的高速晶片介面及系統設計實踐經驗，Rambus 已經在進階介面及系統方面發展了基礎創新技術。Rambus 技術最初用於記憶體市場，現在這些技術廣泛用於高速晶片介面及系統，為客戶提供了效能和成本優勢。這些創新涵蓋的領域包括邏輯介面和控制器介面、記憶體架構、高速平行和序列連結以及系統設計。Rambus 工程師發展的創新已經產生了超過 692 項美國和國際專利，以及超過 547 項等待批准的專利。

Rambus 在晶片介面、系統設計及封裝方面的創新範例

16X Data Rate 16X Data Rate is a technology that transfers 16 bits of data per clock cycle, 8 times as many data bits as DDR (Double Data Rate) techniques used in many DRAMs today and twice the bit transfer rate of XDR memory. This technology allows the XDR2 memory system to run at data rates as high as 12.8Gbps at relatively low and economical system clock speeds.
32X Data Rate Transfers 32 bits of data per I/O on each clock cycle - 16 times as many data bits as the DDR (double data rate) techniques common in many DRAM products today. 32X Data Rate was developed through the Rambus Terabyte Bandwidth Initiative.
Asymmetric Equalization Enables very high bandwidths on next generation memory systems. Signal equalization is applied asymmetrically across the memory controller - DRAM communication link and improves overall signal integrity while minimizing the complexity and cost of the DRAM device. Asymmetric Equalization was developed through the Rambus Terabyte Bandwidth Initiative.
DRAM 上的 DLL/PLL 透過最佳化輸入/輸出 (IO) 時序，提高記憶體系統的最大運作頻率。
DRSL 低電壓、低功耗、差分訊號標準，採用連線 XIO™ 單元與 XDR™ DRAM 裝置的可擴展多 GHz、雙向以及點對點資料匯流排。
Dynamic Point-to-Point Technology Enhanced Enables the performance, scalability and capacity needs of next generation memory systems. DPP supports FlexLink™ C/A allowing dynamic point-to-point capability for command/address signals. DPP enables the scaling of memory system capacity and access granularity. Enhanced DPP was developed through the Rambus Terabyte Bandwidth Initiative.
Enhanced FlexPhase™ Timing Adjustments Enables flexible phase relationships between signals, allowing precise on-chip alignment of data with clock. FlexPhase enhancements improve the sensitivity and capability of FlexPhase for very high performance memory systems operating at data rates of 10 Gbits and higher. Enhanced FlexPhase was developed through the Rambus Terabyte Bandwidth Initiative.
FlexLink™ C/A Interface Industry's first full-speed, scalable point-to-point command/address channel. FlexLink C/A provides the command and address information to a DRAM using a single, differential high speed communications channel. FlexLink C/A was developed through the Rambus Terabyte Bandwidth Initiative.
FlexPhase™ Timing Adjustments Enables flexible phase relationships between signals, allowing precise on-chip alignment of data with clock. FlexPhase technology is a key technology ingredient for achieving high data rates on chip to chip systems that reference an external clock signal. In addition, FlexPhase timing adjustments, which can be particularly beneficial in Fly-by architecture, eliminate many timing offsets associated with process variations, driver/receiver mismatch, on-chip clock skew and clock standing wave effects. FlexPhase technology's automatic centering of data and clock offers designers a quick and easy design solution for high speed chip interconnections.
Fly-by Command and Address Fly-by command/address architectures improve signal integrity in memory systems, thus enabling higher per-pin bit rates and systems capable of GHz data rates. When used in combination with FlexPhase™ circuits that deskew the timing of source synchronous signals, the Fly-by command/address architecture increases memory bandwidth, maintains low latency, and avoids the need for clock-encoding. Fly-by architectures have been used in Rambus memory systems to enable scalability without compromising data rates.
Fully Differential Memory Architecture (FDMA) Industry's first memory architecture that incorporates differential signaling technology on all key signal connections between the memory controller and the DRAM. FDMA enables higher speed, lower noise and lower power in high performance memory systems. FDMA was developed through the Rambus Terabyte Bandwidth Initiative.
Jitter Reduction Technology Improves the signal integrity of very high speed communications links. By reducing jitter, memory signaling performance of 16Gbps can be achieved, enabling the terabyte bandwidth performance levels of next generation memory systems. Jitter Reduction Technology was developed through the Rambus Terabyte Bandwidth InitiativeTerabyte Bandwidth Initiative.
Micro-threading Reduce row and column access granularity resulting in a significant performance benefit for applications dealing with small data objects.
On Die Termination (ODT) Calibration Incorporates On Die Termination impedance improving the signaling environment by reducing the electrical discontinuities introduced with off-die termination.
Output Driver Calibration Improves data rates and system voltage margin by maintaining stable current or voltage drive levels referenced to a precision external resistor.
低電容 ESD 具有強大的靜電放電 (ESD) 保護功能時，減小電容可啟用更高頻率的運作。
八倍速率傳輸 在每個時鐘週期內傳輸 8 位元資料，是當今最先進的採用 DDR﹝雙倍速率傳輸﹞記憶體技術的四倍。
具有快速回復功能的數位 CDR 在低耗電狀態下，用低延遲解決方案啟用快速恢復。
動態點對點技術 在保持高效能點對點訊號傳輸的情況下，允許記憶體升級和擴充容量。
反射取消 提高具有較大阻抗不連續性環境中的系統空餘。
可寫入暫存器 透過用軔體設定最佳化系統參數，降低系統成本。
可程式讀取延遲 透過有效安排內部記憶體時序，使記憶體元件以更高的頻率工作。
可變的爆發存取長度 透過允許 DRAM 和快閃記憶體中每個記憶體讀/寫要求傳送不同數量的資料，提高資料傳輸效率。
基於相位內插器的 CDR 降低成本、功耗及時鐘與資料回復電路的尺寸，改善高速平行和序列連結相對 PLL 時鐘和資料回復 (CDR) 的抖動幅度。
多倍速率傳輸 提高介面的傳輸速率，而無需提高系統時鐘速度。
完全同步的 DRAM 獲得 DRAM 系統的精確時序，提高記憶體傳輸效率，簡化系統管線。
寫入選通終止 允許記憶體控制器寫入任意爆發存取長度的資料，以提高匯流排效率。
寬頻範圍 PLL 利用連續、寬頻調整功能簡化平行和序列連結應用程式。
延遲寫入/寫入延遲 透過減少記憶體核心中的寫讀交接，提高記憶體裝置的傳輸量。
時鐘倍增 DLL 提高高速平行和序列連結的整合水準和抗負載干擾能力。
核心預取 提高介面頻寬，同時允許核心在較低頻率下運作。
模組接頭補償 利用模組接頭減小電互聯中的阻抗不連續性，從而提高系統運作頻率。
模組開關路由 在允許系統升級的同時，降低模組和接頭的成本與管腳數。
模組阻抗補償 透過減小焊接裝置負載所引起的不連續性，提高模組的運作頻率。
用於底板的多級訊號 提高頻率有限通道中所用的高速平行和序列連結的資料傳輸速率和系統空餘。
系統內 IO 空餘和特性 透過測量用於速度分級的訊號完整性參數，提高系統可靠性及系統效能。透過使用系統內電壓及時序空餘測試進行通道診斷，提高通道空餘及可測試性。
系統飛行時間分級 啟用以高頻率運轉的、超大容量匯流排記憶體或邏輯系統。利用控制器邏輯簡化讀/寫安排。
緩衝模組 增加系統的記憶體容量。透過匯集數台低速記憶體裝置的輸出，產生高記憶體頻寬。
自動預充電 透過取消傳送預充電指令的需求，提高記憶體運作效率。
通道均等 透過減少高速平行和序列連結通道內的碼間干擾 (ISI)，提高接收視訊品質及系統空餘。
針對 Multi-Gbps 平台的低功耗創新技術 針對高性能 Multi-Gbps 串列連結的低功耗技術
雙倍匯流排頻率 使記憶體核心的傳輸速率加倍，而無需更高的系統時鐘速度。
雙倍速率傳輸寫入遮罩 允許記憶體控制器設定地址並寫入小於程控爆發存取長度的資料。
雙迴路 PLL/DLL 使用 PLL/DLL 可以降低功耗、矽面積以及整合電路的成本。分享主要通用電路時，允許 PLL/DLL 鎖定至多個任意相位。

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