Enhanced FlexPhase™ Timing Adjustments

Background

Advanced memory solutions, including Rambus' XDR™2 memory architecture, utilize Enhanced FlexPhase™ technology to achieve increased per pin signaling rates at operation in excess of 6.4Gbps. Enhanced FlexPhase technology anticipates the phase difference between signals on different traces and manages the transmission of data bits so that the data arrives at the memory device with a known timing relationship with respect to the command and address signals sent to the memory device. Enhanced FlexPhase can also be used to enhance conventional DRAM architectures by managing the variation in signal propagation times due to variations in trace lengths.

Rambus Solutions

Enhanced FlexPhase improves system data rates by optimizing IO signal timing for improved timing margins and eliminating requirements for trace length matching in data and command/address signal paths. Building on the innovations of FlexPhase technology, Enhanced FlexPhase adds:

• New circuit innovations to increase phase linearity and tighten timing resolutions over previous FlexPhase techniques.
• Innovative timing calibration algorithms for optimizing phase settings of the command/address signals at initialization and in active operation.
• Methods to statistically measure bit error rate (BER) at low enough magnitudes to account for all deterministic jitter (DJ) sources
• Ability to measure BER during characterization of the memory system

Enhanced FlexPhase technology eliminates the need to match trace lengths both on the circuit boards supporting the memory system and within the packages for the memory devices. Such system simplification allows greater flexibility by lowering board and packaging costs. Enhanced FlexPhase also improves overall system timing by eliminating many timing offsets through dynamic compensation for process variations, on-chip clock skew, driver/receiver mismatch and clock standing wave effects. Enhanced FlexPhase brings these system benefits at signaling rates in excess of 6.4Gbps. Enhanced FlexPhase circuit technology brings flexibility, simplicity, and savings to memory system design while enabling extremely high signaling speeds.

Enhanced FlexPhase circuits can also be used to finely tune the timing relationships between data, command, address and clock signals. In conventional DRAM architectures, Enhanced FlexPhase circuits can be used to deskew incoming signals at the controller in order to compensate for uncertainty in the arrival times of signals. Further, Enhanced FlexPhase circuits can be used to intentionally inject a timing offset – "preskew" data such that the data will arrive at the DRAM devices coincident with the command/address or clock signal. Enhanced FlexPhase circuits are equally applicable to point-to-point command and address signals. Enhanced FlexPhase minimizes the systematic timing errors in typical memory systems by adjusting transmit and receive phase offsets at each pin or pin-group.

When used with FlexLink™C/A, Enhanced FlexPhase allows for the differential point-to-point command and address signals to operate at full speed relative to the data. Enhanced FlexPhase preskews C/A signals from the controller to arrive in phase at the DRAM device. The need for trace length matching of C/A signals is eliminated while compensating for systematic timing errors. Optimizing phase settings on the C/A signals is challenging particularly during system boot-up when the DRAM and controller operating states are not fully initialized. Enhanced FlexPhase incorporates calibration algorithms that establishes the communication of the C/A signal and accelerates the search for the optimal phase value. In active operation, Enhanced FlexPhase can also periodicially fine-tune the timing of the C/A signals without disturbing the operational state of the DRAMs.

As in FlexPhase, Enhanced FlexPhase departs from traditional serial link technologies in which timing deskew is performed using an embedded clock. Such deskewing techniques, which rely on encoding schemes such as 8b/10b to ensure adequate transition density for clock recovery, require more chip area, have added power consumption, increased latency, and suffer a bandwidth penalty such as the 20 percent associated with the 8b/10b encoding.

Enhanced FlexPhase includes in-system timing characterization and self-test functionality that enables aggressive timing resolutions in high performance memory systems. Enhanced FlexPhase is incorporated in Rambus' XDR2 leadership memory system with timing resolutions of 1.25ps at data rates of 6.4Gbps. Achieving this level of timing resolution requires innovative edge-placement circuitry with a linear range of programmable adjustments. Enhanced FlexPhase provides a continuous range of timing adjustments. Precision circuitry adjusts FlexPhase timing value with a clock cycle while levelization logic provides adjustments over multiple clock cycles.

Enhanced FlexPhase™ Operation

During READ access operations in an example XDR2 system, a memory controller incorporating Enhanced FlexPhase technology determines and stores the "receive" phase difference between the transmitted control signals and the data received from each memory device. The phase difference corresponding to each memory device is subsequently used to deskew the data signals which arrive at the memory controller at different times, thereby allowing proper reconstitution of the data accessed from each of the memory devices.

During WRITE operations, a similar process is performed where a "transmit" phase difference is determined for each memory device and stored within the memory controller. Those transmit phase differences are then used to modify (preskew) the timing delay between the transmitted command/address signals and the data sent to each memory device.

During both READ and WRITE operations, Enhanced FlexPhase, when used in FlexLink C/A, preskews command and address signals sent from the controller to arrive in phase at the corresponding memory device. As with the data circuits, Enhanced FlexPhase C/A circuits are implemented on the controller side of the signal path to keep memory device costs and complexity low.

Enhanced FlexPhase circuitry can be coupled with data analysis software to measure bit error rate (BER). The high precision circuitry combined with an innovative calibration algorithm measures successful data transmission at various phase offsets. Through periodic measures, Enhanced FlexPhase circuitry enables the controller to collect the data needed to statistically determine BER at resolutions that capture deterministic jitter sources such as pattern dependent inter-symbol interference (ISI), duty cycle distortion, periodic jitter, as well as random jitter.

Benefits

Device Benefits:

At data rates above 6.4Gbps, Enhanced FlexPhase helps to compensate for the manufacturing variations that degrade timing windows and operational performance of the memory. Enhanced FlexPhase technology allows memory interfaces to operate at these high data rates without the power, area and latency penalties incurred in systems using Clock and Data Recovery (CDR) techniques. Enhanced FlexPhase also provides for improved testability by using digital phase offsets for margin testing of the high speed chip interfaces.

System Benefits:

Enhanced FlexPhase technology relaxes PCB trace length matching requirements by anticipating and calibrating the signaling phase offsets caused by variations in trace lengths and impedances. Enhanced FlexPhase timing adjustments allows much simpler, more compact and cost-efficient memory layouts. Enhanced FlexPhase timing adjustments provide for in-system test and characterization of key data and command/address signals, thereby enabling performance testing of the high speed links. Enhanced FlexPhase enables designers to statistically characterize the BER of the memory channel.