FlexLink™ C/A Interface

Summary

FlexLink™ C/A interface is a full-speed, scalable, point-to-point command/address (C/A) interface technology that provides flexible access granularity and scalability. Using the FlexLink C/A interface, the C/A channel can be implemented with as a little as two wires per DRAM device. The technology's serial connectivity reduces area, power and pin count, and lowers overall system costs.

When combined with Rambus' 16X Data Rate and Fully Differential Memory Architecture technologies, the FlexLink C/A interface can enable data rates of 12.8Gbps with only a single differential C/A link between the memory controller and DRAM component. In comparison, contemporary DDR2 components with densities greater than 1 Gbit require a minimum of 28 wires to implement the C/A interface between the memory controller and DRAM component.

What is the FlexLink C/A interface?

The FlexLink C/A interface implements a full C/A channel in as few as a single, point-to-point, differential signal link. With this architecture, the C/A channel can run at the full DQ rate. In the XDR™2 memory architecture, C/A and DQ channels operate at data rates of up to 12.8Gbps.

Traditional industry standard memory architectures that use much slower data rates scale bandwidth through wide busses and multi-drop C/A channels. Wide, multi-drop interfaces require significantly more signals, which in turn increases wire and pin count density, and increases power requirements. In addition, the cost of replicating wide C/A channels is high. These disadvantages make scaling of wide busses increasingly impractical. In comparison, scaling of fast and narrow FlexLink C/A channels minimizes costs and power requirements. The Rambus Flexlink C/A interface provides data rate improvements to high-speed interfaces over conventional wide busses which are commonly used in today's industry main memory and graphics memories.

The FlexLink C/A interface provides for straightforward capacity scaling while maintaining access granularity. An example is a memory system having four independent C/A channels and 32 DQ links supporting 32-byte access granularity. Such a system can employ one, two or four DRAM devices, maintaining system bandwidth and 32-byte access granularity while offering the capability of scaling memory capacity by a factor of four.

In addition, the FlexLink C/A interface offers support for scalable access granularity. A controller can be attached to a single DRAM through one, two or four independent C/A channels and 32 DQ links supporting either 128-, 64- or 32-byte access granularity, respectively.

The FlexLink C/A interface's point-to-point architecture allows optimum wire termination characteristics. Rather than implementing a compromise equalization setting to support multiple receivers, the FlexLink C/A interface allows the controller's transmission equalization to be optimized for an individual receiver. Optimizing wire terminations and controller transmission equalization helps to minimize jitter and the bit error rate (BER) and be used in conjunction with implementations of Rambus's 16X Data Rate technology.

Commercial and Performance Benefits

• FlexLink C/A interface's point-to-point topology allows C/A channels to run at the full DQ data rate.
• FlexLink C/A interface allows for simple capacity scaling or access granularity scaling without complex controller connections. This means designers need not compromise access granularity for capacity increases.
• FlexLink C/A interface's high speed, point-to-point architecture dramatically reduces the number of wires, simplifying hardware, lowering power consumption and holding down costs.
• FlexLink C/A interface's optimized wire terminations and controller transmission equalization minimize jitter and BER.

FlexLink C/A interface is a development of Rambus' Terabyte Bandwidth Initiative. The Terabyte Bandwidth initiative is driving the development of signaling technologies needed for future memory architectures capable of delivering a terabyte per second of memory bandwidth to a single System-on-Chip (SoC) device.