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Fully Differential Memory Architecture (FDMA)SummaryRambus' Fully Differential Memory Architecture (FDMA) provides enhanced signal integrity and noise immunity when compared to single-ended memory architectures. This high-quality signaling technology enables very high-speed data transmission and excellent memory bandwidth performance. FDMA implements fully-differential signaling - using a point-to-point topology - for command/address (C/A), clock (CLK) and data (DQ) channels. This technology builds on the foundation of the high-speed differential signaling for DQ and CLK channels used in the XDR™ memory architecture. Differential signaling provides robust communication between the memory controller and DRAM components. It inherently reduces interference noise from simultaneous switching outputs (SSO) and crosstalk. Further, differential signaling reduces the EMI that would otherwise be generated in a single-ended system operating at the same data rate or frequency. When combined with Rambus' 16X Data Rate technology, FDMA enables C/A and DQ channels to operate at signaling speeds of 12.8Gbps with a 800MHz external clock. What is differential signaling?Conventional industry standard memory architectures use single-ended signaling whereby a voltage on the signal wire is compared with a reference voltage (usually ground) on another wire. If the measured voltage, within margin, is at the power supply voltage, the signal is considered a "1"; and if the measured voltage is below a marginal threshold of the reference voltage it is considered a "0". Single-ended signaling is simple to implement, but has limited noise immunity at the low voltages typical of modern electronics. It is also prone to crosstalk from the inductive coupling caused by sharing the same return line. In high-speed systems, these disadvantages will collectively manifest as errors, as measured by the Bit Error Ratio (BER). Differential signaling uses two lines for each signal. A complementary signal is transmitted on one line or the other - depending on the logic level required - using a small DC current. The current is passed through a resistor on each line to generate a voltage, the difference being measured at the receiver. Depending on the polarity, the signal is interpreted as a "1" or "0". Simultaneous Switching Output (SSO) noise - a function of the cumulative value of the total amount of current change - is also reduced because the same amount of current is generated regardless of whether the bit is a "1" or "0". 
The advantage of differential signaling is that for a given voltage at the transmitter, twice the voltage difference is measured at the receiver (the difference in voltage between the two wires in the current loop). This compares with single-ended signaling that exhibits the same voltage at the transmitter and receiver (the difference between the voltage on the wire and ground, namely 0 V). Twice the voltage at the receiver means it takes twice as much noise to go beyond the threshold of a valid voltage level. Further, differential signaling has superior noise immunity when compared to single-ended signaling due to its inherent common mode noise rejection. Any voltage noise that couples into one leg of an adjacent pair is likely to couple into the other leg. Because the difference between the two signals is measured at the receiver the noise components common to each leg are effectively cancelled out. In addition to being less susceptible to noise, differential signal pairs create less EMI than single-ended signals. This is because changes in signal level in the two wires create opposing electromagnetic fields that superimpose to cancel each other out, reducing crosstalk and spurious emissions. What is Fully Differential Memory Architecture?Conventional industry standard memory architectures such as GDDR and DDR use single-ended signaling for data and command/address. However, as memory speeds have increased, and more traces have been added to PCBs to expand bus width, noise and crosstalk have become major challenges. Rambus introduced differential signaling for DQ and CLK channels in the Rambus XDR™ memory architecture. Single-ended signaling was retained for C/A lines, in the Rambus XDR memory architecture to reduce noise and crosstalk. However, 16X Data Rate technology benefits from differential signaling in DQ, CLK and C/A lines, thereby leading to Fully Differential Memory Architecture (FDMA). 
Differential signaling uses two wires per channel. In contrast, single-ended systems use a single wire per channel and a shared ground wire for all channels. Differential signaling's benefits are greatest at multi-Gbps data rates. At these speeds, single-ended systems are increasingly limited by physical phenomena such as SSO and cross-talk from inductive coupling. Further, at these data rates, differential signaling requires fewer power and ground signals than single-ended techniques. Rambus XDR memory implements differential data signaling whereas industry main memory and graphics memory still employ single-ended data signaling even at data rates up to 6Gbps. Additionally, differential signaling becomes even more compelling when used in conjunction with Rambus' FlexLink™ C/A interface, a two-wire, point-to-point C/A interface. Commercial and Performance Benefits
FDMA is a development of Rambus' Terabyte Bandwidth Initiative. The Terabyte Bandwidth Initiative is driving the development of signaling technologies needed for future memory architectures capable of delivering a terabyte per second of memory bandwidth to a single System-on-Chip (SoC) device. |
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