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File Name: Study of Signal and Power Integrity Challenges in High-Speed Memory I/O Designs Using Single-Ended Signaling Schemes

In contrast to most chip-to-chip I/O interfaces that use differential signaling, the mainstream memory interface designs are based on single-ended signaling such as SSTL or PODL. Extending the data rate for single-ended signaling beyond current data rate of a few Gb/s is becoming very difficult. This paper studies the impact of various signal and power noise components on the potential data rate of single-ended signaling systems. Although our discussion covers general single-ended signaling systems, GDDR3/4 memory systems are considered as detailed examples. In particular, the performance of various packages, motherboards, coding schemes, and equalization techniques are evaluated. We show that the crosstalk impact can be mitigated by employing stripline designs, incurring high cost in system design. However, the potential data rate is still limited by SSO noise. The DBI coding technique recently introduced in GDDR4 reduces SSO noise significantly but the final system performance gain is marginal after accounting for the pin overhead. Finally, a relative performance gain using various different single-ended signaling options is given and compared with an equivalent differential system.

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