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16X Data Rate
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16X Data Rate is a technology that transfers 16 bits of data per clock cycle, 8 times as many data bits as DDR (Double Data Rate) techniques used in many DRAMs today and twice the bit transfer rate of XDR memory. This technology allows the XDR2 memory system to run at data rates as high as 12.8Gbps at relatively low and economical system clock speeds. |
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32X Data Rate
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Transfers 32 bits of data per I/O on each clock cycle - 16 times as many data bits as the DDR (double data rate) techniques common in many DRAM products today. 32X Data Rate was developed through the Rambus Terabyte Bandwidth Initiative. |
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Advanced Power State Management (APSM)
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Advanced Power State Management (APSM) reduces memory system power and provides ultra-fast transition times between various low-power and active operating modes. |
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Asymmetric Equalization
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Enables very high bandwidths on next generation memory systems. Signal equalization is applied asymmetrically across the memory controller - DRAM communication link and improves overall signal integrity while minimizing the complexity and cost of the DRAM device. Asymmetric Equalization was developed through the Rambus Terabyte Bandwidth Initiative. |
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Auto Precharge
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Increases efficiency of memory operations by eliminating the need to send precharge commands. |
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Buffered Modules
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Increases memory capacity of a system. Produces high memory bandwidth by aggregating the output of several lower-speed memory devices. |
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Channel Equalization
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Improves receive eye and system margins by reducing Inter-Symbol Interference (ISI) in high speed parallel and serial link channels. |
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Clock Multiplying DLL
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Improves integration levels and noise rejection capability for high speed parallel and serial links. |
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Core Prefetch
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Improves interface bandwidth while allowing the core to operate at a lower frequency. |
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Digital CDR with Fast Recovery
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Enables fast recovery with low-latency from a low-power state. |
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DLL/PLL on a DRAM
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Improves maximum operating frequency of a memory system by optimizing Input/Output (IO) timing. |
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Double Bus Rate Technology
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Doubles the transfer rate out of a memory core without the need for higher system clock speeds. |
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Double Data Rate Write Masking
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Allows a memory controller to address and write data whose size is smaller than the programmed burst length. |
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DRSL
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A low-voltage, low-power, differential signaling standard that enables the scalable multi-GHz, bi-directional, and point-to-point data busses that connect the XIO™ cell to XDR™ DRAM devices. |
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Dual Loop PLL/DLL
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Reduces power, silicon area, and cost of an integrated circuit using a PLL/DLL. Allows a PLL/DLL to lock to several arbitrary phases while sharing critical common circuitry. |
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Dynamic Point-to-Point Technology
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Enables memory upgrades and expandable capacity while maintaining high-performance point-to-point signaling. |
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Dynamic Point-to-Point Technology Enhanced
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Enables the performance, scalability and capacity needs of next generation memory systems. DPP supports FlexLink™ C/A allowing dynamic point-to-point capability for command/address signals. DPP enables the scaling of memory system capacity and access granularity. Enhanced DPP was developed through the Rambus Terabyte Bandwidth Initiative. |
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Enhanced FlexPhase™ Timing Adjustments
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Enables flexible phase relationships between signals, allowing precise on-chip alignment of data with clock. FlexPhase enhancements improve the sensitivity and capability of FlexPhase for very high performance memory systems operating at data rates of 10 Gbits and higher. Enhanced FlexPhase was developed through the Rambus Terabyte Bandwidth Initiative. |
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FlexClocking™ Architecture
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FlexClocking technology is an architecture that utilizes asymmetric partitioning and places critical calibration and timing circuitry in the controller interface, greatly simplifying the design of the DRAM interface. |
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FlexLink™ C/A Interface
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Industry's first full-speed, scalable point-to-point command/address channel. FlexLink C/A provides the command and address information to a DRAM using a single, differential high speed communications channel. FlexLink C/A was developed through the Rambus Terabyte Bandwidth Initiative.
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FlexPhase™ Timing Adjustments
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Enables flexible phase relationships between signals, allowing precise on-chip alignment of data with clock. FlexPhase technology is a key technology ingredient for achieving high data rates on chip to chip systems that reference an external clock signal. In addition, FlexPhase timing adjustments, which can be particularly beneficial in Fly-by architecture, eliminate many timing offsets associated with process variations, driver/receiver mismatch, on-chip clock skew and clock standing wave effects. FlexPhase technology's automatic centering of data and clock offers designers a quick and easy design solution for high speed chip interconnections. |
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Fly-by Command and Address
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Fly-by command/address architectures improve signal integrity in memory systems, thus enabling higher per-pin bit rates and systems capable of GHz data rates. When used in combination with FlexPhase™ circuits that deskew the timing of source synchronous signals, the Fly-by command/address architecture increases memory bandwidth, maintains low latency, and avoids the need for clock-encoding. Fly-by architectures have been used in Rambus memory systems to enable scalability without compromising data rates. |
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Fully Differential Memory Architecture (FDMA)
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Industry's first memory architecture that incorporates differential signaling technology on all key signal connections between the memory controller and the DRAM. FDMA enables higher speed, lower noise and lower power in high performance memory systems. FDMA was developed through the Rambus Terabyte Bandwidth Initiative.
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Fully Synchronous DRAM
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Allows precise timing from a DRAM system, improves memory transfer efficiency, and facilitates system pipelining. |
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In-System IO Margin and Characterization
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Improves system reliability and system yields by measuring signal integrity parameters used for speed binning. Improves channel margins and testability by using in-system voltage and timing margin testing for channel diagnostics. |
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Jitter Reduction Technology
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Improves the signal integrity of very high speed communications links. By reducing jitter, memory signaling performance of 16Gbps can be achieved, enabling the terabyte bandwidth performance levels of next generation memory systems. Jitter Reduction Technology was developed through the Rambus Terabyte Bandwidth InitiativeTerabyte Bandwidth Initiative. |
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Late Write/Write Latency
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Improves throughput of a memory device by reducing write-to-read turnaround within the memory core. |
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Low-Capacitance ESD
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Reduces capacitance to enable higher-frequencies of operation while maintaining robust electrostatic discharge (ESD) protection. |
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Low-Power Initiative For Multi-Gbps Platforms
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Low-power techniques for high performance multi-Gbps serial links |
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Micro-threading
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Reduce row and column access granularity resulting in a significant performance benefit for applications dealing with small data objects. |
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MicroLens™ Optical Design Technology
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Provides optimum utilization of high-brightness LEDs in edge-lit lighting applications delivering superior brightness and uniformity of illumination. |
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Module Connector Compensation
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Improves operating frequency of systems utilizing module connectors by mitigating the impedance discontinuity of the electrical interconnection. |
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Module Impedance Compensation
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Improves operating frequency of a module by mitigating the discontinuity caused by soldered-on device loading. |
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Module On-Off Routing
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Lowers cost and pincount of modules and connectors while allowing system upgrades. |
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Module Threading
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Module Threading improves the throughput and power efficiency of a memory module by applying parallelism to module data accesses. |
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Multi-Data-Rate Transfer
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Increases the transfer rate of an interface without the need for higher system clock speeds. |
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Multi-Level Signaling Applied to Backplanes
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Improves data rates and systems margins in high-speed parallel and serial links used in frequency limited channels. |
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Near Ground Signaling
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Near Ground Signaling (NGS) is a single-ended, ground-terminated signaling technology that enables high data rates at significantly reduced IO signaling power and design complexity, while maintaining excellent signal integrity. |
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Octal Data Rate
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Transfers eight bits of data on each clock cycle, four times as many as today's state-of-the-art memory technologies that use DDR (Double Data Rate). |
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On Die Termination (ODT) Calibration
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Incorporates On Die Termination impedance improving the signaling environment by reducing the electrical discontinuities introduced with off-die termination. |
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Output Driver Calibration
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Improves data rates and system voltage margin by maintaining stable current or voltage drive levels referenced to a precision external resistor. |
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Phase Interpolator Based CDR
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Reduces cost, power, and area of a clock and data recovery circuit, and improves jitter performance in high-speed parallel and serial links versus PLL clock and data recovery (CDRs). |
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Programmable Read Latency
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Allows a memory component to operate at higher frequencies by more efficiently scheduling internal memory timings. |
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Reflection Cancellation
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Improves system margins in environments with large impedance discontinuities. |
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System Flight Time Levelization
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Enables very large capacity bussed memory or logic systems which operate at high frequency. Simplifies read/write scheduling from the controller logic. |
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Variable Burst Length
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Improves data transfer efficiency by allowing varying amounts of data to be sent per a memory read or write request in DRAMs and Flash memory. |
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Very Low-Swing Differential Signaling
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Very Low-Swing Differential Signaling (VLSD) is a bi-directional, ground-referenced, differential signaling technology which offers a high-performance, low-power, and cost-effective solution for applications requiring extraordinary bandwidth and superior power efficiency. |
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Wide Frequency Range PLL
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Simplifies parallel and serial link applications with continuous, wide-range frequency adjustment capability. |
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Write Strobe Terminate
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Allows a memory controller to write data bursts of arbitrary lengths, increasing bus efficiency. |
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Writeable Mode Register
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Decreases system cost by setting optimal system parameters by firmware. |
