XDR™ Memory Architecture:
The Picture-Perfect Solution for HDTV

Texas Instruments DLP® projectors are the latest digital consumer electronics products to take advantage of the breakthrough performance of Rambus' XDR™ memory architecture. With the XDR memory architecture, DLP projectors provide unmatched image quality and stunning color, and are ideal for displaying movies, sports, games or digital photos in up to 1080p resolution.

"The XDR memory architecture and its innovative technologies are key enablers of the razor-sharp images and excellent reproduction of fast-motion video made possible by the advanced DLP chip architecture," said Lars Yoder, vice president and manager, Front Projection Business Unit, DLP Products, Texas Instruments Incorporated. "The Rambus engineering teams supported us with complete services from design through production helping us make a new generation of amazing DLP projectors a reality."

At the heart of a DLP projector is the DLP chip or Digital Micromirror Device (DMD) with its millions of microscopic mirrors. Image processing and control of the DMD is handled by the sophisticated DLP ASIC and DMD control IC. This ASIC incorporates a 2-Byte wide XIO interface which connects to a single 512Mb XDR DRAM. A single XDR DRAM provides all the necessary bandwidth and capacity to enable the amazing visual performance of the DLP architecture.

XDR Memory Architecture: Ready for the Future of HDTV

Today's High-Definition TVs and projectors provide incredibly rich viewing experiences, but in the future, consumers will expect even more. With requirements for handling multiple streams of HD content, enhanced image processing and motion compensation tasks, 10-bit color and more, HDTV designers need a memory architecture that provides the highest bandwidth performance with the fewest devices. Rambus' XDR memory architecture delivers bandwidth of up to 8 GB/s with a single XDR DRAM device and has a roadmap to device bandwidths of up to 16 GB/s. Current production XDR DRAM devices provide a level of performance suitable for even high-end systems slated for the end of the decade.

Even low-end HDTV systems of the near future will offer 1080p resolutions at 120fps (H.264 HD) with 3-field MADI de-interlacing and motion compensation jitter removal. Such a system would require a memory architecture that delivers a minimum peak bandwidth of 2.6 GB/s. With currently available DRAM, a low-end system would require two DDR2 512Mbit x16 800MHz devices or just a single XDR DRAM device. Bandwidth requirements for a mid-range system employing motion compensation technology such as Digital Natural Motion would rise to 4.6 GB/s while requiring 64Mbytes of capacity. Again, currently available XDR DRAM could meet this need with a single device while three DDR2 800 devices would be required and add the complexity of an asymmetric memory subsystem. In future high-end systems, with multiple HD streams, advanced motion compensation and 3D graphics capabilities, bandwidth requirements could rise to 10 GB/s and above. The XDR memory architecture could meet even this demanding requirement with just two XDR 512Mbit 4GHz devices or a single 1Gbit 6.4GHz device on the roadmap.

Learn more about the XDR memory architecture.