Innovations

With over fifteen years of experience in high-speed chip interface and system design, Rambus has developed fundamental innovations for advanced interfaces and systems. Originally applied to the memory market, Rambus technologies are now used in a broad range of high-speed chip interfaces and systems, providing customers with performance and cost advantages. These innovations span the areas of logic and controller interfaces, memory architecture, high-speed parallel and serial links, and system design. Innovations developed by Rambus engineers have resulted in more than 692 U.S. and international patents, and more than 547 patent applications.

Examples of Rambus Innovations in Chip Interfaces, System Design, and Packaging

32X Data Rate Transfers 32 bits of data per I/O on each clock cycle - 16 times as many data bits as the DDR (double data rate) techniques common in many DRAM products today. 32X Data Rate was developed through the Rambus Terabyte Bandwidth Initiative.
Asymmetric Equalization Enables very high bandwidths on next generation memory systems. Signal equalization is applied asymmetrically across the memory controller - DRAM communication link and improves overall signal integrity while minimizing the complexity and cost of the DRAM device. Asymmetric Equalization was developed through the Rambus Terabyte Bandwidth Initiative.
Auto Precharge Increases efficiency of memory operations by eliminating the need to send precharge commands.
Buffered Modules Increases memory capacity of a system. Produces high memory bandwidth by aggregating the output of several lower-speed memory devices.
Channel Equalization Improves receive eye and system margins by reducing Inter-Symbol Interference (ISI) in high speed parallel and serial link channels.
Clock Multiplying DLL Improves integration levels and noise rejection capability for high speed parallel and serial links.
Core Prefetch Improves interface bandwidth while allowing the core to operate at a lower frequency.
Digital CDR with Fast Recovery Enables fast recovery with low-latency from a low-power state.
DLL/PLL on a DRAM Improves maximum operating frequency of a memory system by optimizing Input/Output (IO) timing.
Double Bus Rate Technology Doubles the transfer rate out of a memory core without the need for higher system clock speeds.
Double Data Rate Write Masking Allows a memory controller to address and write data whose size is smaller than the programmed burst length.
DRSL A low-voltage, low-power, differential signaling standard that enables the scalable multi-GHz, bi-directional, and point-to-point data busses that connect the XIO™ cell to XDR™ DRAM devices.
Dual Loop PLL/DLL Reduces power, silicon area, and cost of an integrated circuit using a PLL/DLL. Allows a PLL/DLL to lock to several arbitrary phases while sharing critical common circuitry.
Dynamic Point-to-Point Technology Enables memory upgrades and expandable capacity while maintaining high-performance point-to-point signaling.
Dynamic Point-to-Point Technology Enhanced Enables the performance, scalability and capacity needs of next generation memory systems. DPP supports FlexLink™ C/A allowing dynamic point-to-point capability for command/address signals. DPP enables the scaling of memory system capacity and access granularity. Enhanced DPP was developed through the Rambus Terabyte Bandwidth Initiative.
FlexLink™ C/A Industry's first full-speed, scalable point-to-point command/address channel. FlexLink C/A provides the command and address information to a DRAM using a single, differential high speed communications channel. FlexLink C/A was developed through the Rambus Terabyte Bandwidth Initiative.
FlexPhase™ Timing Adjustments Enables flexible phase relationships between signals, allowing precise on-chip alignment of data with clock. FlexPhase technology is a key technology ingredient for achieving high data rates on chip to chip systems that reference an external clock signal. In addition, FlexPhase timing adjustments, which can be particularly beneficial in Fly-by architecture, eliminate many timing offsets associated with process variations, driver/receiver mismatch, on-chip clock skew and clock standing wave effects. FlexPhase technology's automatic centering of data and clock offers designers a quick and easy design solution for high speed chip interconnections.
FlexPhase™ Timing Adjustments Enhanced Enables flexible phase relationships between signals, allowing precise on-chip alignment of data with clock. FlexPhase enhancements improve the sensitivity and capability of FlexPhase for very high performance memory systems operating at data rates of 10 Gbits and higher. Enhanced FlexPhase was developed through the Rambus Terabyte Bandwidth Initiative.
Fly-by Command and Address Fly-by command/address architectures improve signal integrity in memory systems, thus enabling higher per-pin bit rates and systems capable of GHz data rates. When used in combination with FlexPhase™ circuits that deskew the timing of source synchronous signals, the Fly-by command/address architecture increases memory bandwidth, maintains low latency, and avoids the need for clock-encoding. Fly-by architectures have been used in Rambus memory systems to enable scalability without compromising data rates.
Fully Differential Memory Architecture (FDMA) Industry's first memory architecture that incorporates differential signaling technology on all key signal connections between the memory controller and the DRAM. FDMA enables higher speed, lower noise and lower power in high performance memory systems. FDMA was developed through the Rambus Terabyte Bandwidth Initiative.
Fully Synchronous DRAM Allows precise timing from a DRAM system, improves memory transfer efficiency, and facilitates system pipelining.
In-System IO Margin and Characterization Improves system reliability and system yields by measuring signal integrity parameters used for speed binning. Improves channel margins and testability by using in-system voltage and timing margin testing for channel diagnostics.
Jitter Reduction Technology Improves the signal integrity of very high speed communications links. By reducing jitter, memory signaling performance of 16Gbps can be achieved, enabling the terabyte bandwidth performance levels of next generation memory systems. Jitter Reduction Technology was developed through the Rambus Terabyte Bandwidth InitiativeTerabyte Bandwidth Initiative.
Late Write/Write Latency Improves throughput of a memory device by reducing write-to-read turnaround within the memory core.
Low-Capacitance ESD Reduces capacitance to enable higher-frequencies of operation while maintaining robust electrostatic discharge (ESD) protection.
Low-Power Initiative For Multi-Gbps Platforms Low-power techniques for high performance multi-Gbps serial links
Micro-threading Reduce row and column access granularity resulting in a significant performance benefit for applications dealing with small data objects.
Module Connector Compensation Improves operating frequency of systems utilizing module connectors by mitigating the impedance discontinuity of the electrical interconnection.
Module Impedance Compensation Improves operating frequency of a module by mitigating the discontinuity caused by soldered-on device loading.
Module On-Off Routing Lowers cost and pincount of modules and connectors while allowing system upgrades.
Multi-Data-Rate Transfer Increases the transfer rate of an interface without the need for higher system clock speeds.
Multi-Level Signaling Applied to Backplanes Improves data rates and systems margins in high-speed parallel and serial links used in frequency limited channels.
Octal Data Rate Transfers eight bits of data on each clock cycle, four times as many as today's state-of-the-art memory technologies that use DDR (Double Data Rate).
On Die Termination (ODT) Calibration Incorporates On Die Termination impedance improving the signaling environment by reducing the electrical discontinuities introduced with off-die termination.
Output Driver Calibration Improves data rates and system voltage margin by maintaining stable current or voltage drive levels referenced to a precision external resistor.
Phase Interpolator Based CDR Reduces cost, power, and area of a clock and data recovery circuit, and improves jitter performance in high-speed parallel and serial links versus PLL clock and data recovery (CDRs).
Programmable Read Latency Allows a memory component to operate at higher frequencies by more efficiently scheduling internal memory timings.
Reflection Cancellation Improves system margins in environments with large impedance discontinuities.
System Flight Time Levelization Enables very large capacity bussed memory or logic systems which operate at high frequency. Simplifies read/write scheduling from the controller logic.
Variable Burst Length Improves data transfer efficiency by allowing varying amounts of data to be sent per a memory read or write request in DRAMs and Flash memory.
Wide Frequency Range PLL Simplifies parallel and serial link applications with continuous, wide-range frequency adjustment capability.
Write Strobe Terminate Allows a memory controller to write data bursts of arbitrary lengths, increasing bus efficiency.
Writeable Mode Register Decreases system cost by setting optimal system parameters by firmware.

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