Low-Power Initiative For Multi-Gbps Platforms

Summary

The Rambus low-power initiative for multi-Gbps signaling is an effort to engineer critical Rambus ingredient technologies that enhance the high-performance and low-power design goals of today's multi-Gbps data links. As a result of this initiative, Rambus has been able to reduce power consumption to approximately 2.2mW/Gbps while operating at multi-GHz data rates.

The Rambus approach used to reduce power and improve system performance incorporates innovative silicon, system and software techniques that relate to:

  • Resonant clock distribution networks;
  • Signaling optimizations in the transmitter and receiver;
  • Adaptive equalization of serial links; and
  • Power supply noise rejection.

Through the use of Rambus ingredient technologies, including low-power signaling technologies, aggressive design goals in power and performance can be achieved.

Background

Current high-bandwidth, multi-Gbps serial links require a trade-off between data rate performance and power consumption. As system designers face hard power limits due to thermal or battery-life requirements, optimizing this power versus performance trade-off becomes more critical. Historically, the end goal in multi-Gbps data-rate power consumption has been the 1mW per Gbps metric - current technology achieves approximately 10-20mW per Gbps. Rambus has achieved an aggressive and significant progression towards the elusive 1mW per Gbps target – a serial link, proven in silicon, that boasts 2.2mW per Gbps power dissipation. This is achieved through the use of a shared LC-PLL for reference-clock multiplication, a resonant clock-distribution network, a low-swing voltage-mode transmitter, a low-power phase rotator for the receiver clocks, and software-based CDR and adaptive equalization,

Advanced serial link backplane transceivers have been demonstrated by others in the industry at 20mW/Gb/s* , and chip-to-chip links have more recently achieved power efficiencies near 10mW/Gb/s**.

Rambus has researched and developed circuit and software techniques that deliver significant advances in power efficiency for the serial links without sacrificing the jitter performance or signal integrity features required to operate at an acceptable bit-error rate (BER). These advances provide building blocks capable of enabling the low-power, high data rate applications required in the compute and mobile markets.

Rambus Solution

Rambus' low-power signaling technologies improve system performance through techniques that leverage on-chip features such as:

  • Resonant clock distribution networks;
  • Signaling optimizations in the transmitter and receiver;
  • Adaptive equalization of serial links; and
  • Power supply noise rejection.

Suitable for compute and consumer applications where multi-Gbps data rate requirements are critical to the success of the platforms, low-power signaling technologies from Rambus meet data performance needs while enhancing the thermal/battery life performance of the system. These techniques provide system designers with increased flexibility in their efforts to meet overall system power consumption goals. Rambus' patented and patent pending innovations such as Adaptive Equalization of serial links and Power Supply Noise Rejection in PLLs and DLLs, enable the achievement of the low-power results presented at ISSCC 2007.

Figure1: Clock multiplication and distribution
Figure2: Tramsmitter block diagram

Where Are Benefits Realized?

Device Benefits:

At multi-GHz rates, Rambus' low-power signaling technologies have been used to reduce power consumption to approximately 2.2mW/Gbps. When compared to currently published approaches for 6.25 Gbps IO PHYs, this solution represents a power reduction by a factor greater than three times (3x) that of traditional serial links. This power reduction is realized through the use of energy regenerative clock circuitry to improve overall clocking performance – and optimized differential signal circuitry to minimize the need for high-energy signal drive.

Subsystem Benefits:

Rambus low-power signaling technologies reduce the power consumption per IO PHY, thereby reducing the power requirements for modules and subsystems relying on high-bandwidth devices to implement their data interface objectives. Heat dissipation, cooling requirements of enclosures, battery life, and power-cost management are all advantaged through the use of macro devices leveraging the capabilities of the Rambus low-power solution. Lower power, lower total cost of ownership and sustainable high bandwidth data performance are differentiating advantages to the subsystem customer.

Links:

For additional information on the technical paper presented at ISSCC 2007, please follow these links below.

* K. Krishna, DA Yokoyama-Martin, S Wolfer, et al., "A 0.6 to 9.6Gb/s Binary Backplane Transceiver Core in 0.13μm CMOS," ISSCC Dig. Tech. Papers, vol. 48, pp. 64-65, Feb., 2005.

** E. Prete, D. Sheideler, A. Sanders, "A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next- Generation Memory Interfaces," ISSCC Dig. Tech. Papers, vol. 49, pp. 88-89, Feb., 2006.

*** R. Palmer, J. Poulton, et al, "A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications", ISSCC Dig. Tech Papers, vol. 50, pp. 9-11, Feb., 2007.
Request More Information